1. Field of the Invention
The invention applies to the field of interface circuits connecting memory systems to a bus. The invention is particularly applicable to the field of handling pending memory request signals from a bus.
2. Background Information
A general purpose computer system typically includes a processor, memory, and one or more peripheral devices coupled together by one or more buses. These buses may use asynchronous transmission, isochronous transmission or a combination of the two. Asynchronous transmission places an emphasis on guaranteed delivery of the data. In asynchronous transmission, the recipient of the data, typically a processor acknowledges when asynchronous data has arrived and has been properly written to memory. Isochronous transmission places an emphasis on guaranteed timing of the data. Isochronous data typically has a guaranteed latency in that a packet of data is transferred at predetermined time intervals In isochronous transmission, when data is lost, the data is often not recoverable. Isochronous transmission is often used in real time communications such as video communication systems.
In order to speed up reading and writing to memory, asynchronous transmission includes a protocol defining a subcategory of data called xe2x80x9cphysical packets.xe2x80x9d Typically, a software layer determines how most data packets are handled. However, the software layer is slow. Physical packets bypass the software layer, allowing access to memory via hardware which is faster than the software.
In order to handle physical packets, the device transmitting the data and the device receiving the data must be compatible. Compatible devices usually include hardware and protocols that allow direct reads and writes to specific memory addresses without software intervention. The hardware also generates acknowledge signals to acknowledge receipt of the physical write packet.
Certain specifications, including the IEEE 1394-OHCI (Open Hosts Controller interface) specify two methods of handling a physical packet, containing a write request. In a first method, when a write request is received, the receiving device outputs an acknowledgment pending (xe2x80x9cACK_PENDINGxe2x80x9d) packet or signal indicating that the write request has been received. When processing of the received write request is complete and the data is written to an appropriate section of memory, a response packet, such as an ACK_COMPLETE packet is transmitted.
The IEEE-1394-OHCI specification also defines a second method of handling write requests as a xe2x80x9cposted write.xe2x80x9d When handling posted writes, the hardware of the receiving device transmits an ACK_COMPLETE packet upon receipt of a write request in a physical packet. The received write request is stored in a buffer in the hardware of the receiving device to be executed at a later time. If, at the later time, the data is properly written to memory, no further action needs to be taken because the ACK_COMPLETE packet which was transmitted indicated that the information was already properly written to memory. However, if the receiving device is unable to execute the write request, an error occurs. The software of the receiving device handles the error. The software may re-route the write request. Typically, software in the receiving device transmits an error packet to the originator of the write request indicating that the ACK_COMPLETE packet is invalid and that the data has not been properly written to memory. However, until software clears the error, the buffer maintains the information corresponding to the write request, preventing further receiving of write requests. Because software can be slow, an error in a posted write can significantly slow down operation of the system.
Thus, an improved method of handling physical packets containing write requests is needed.
A circuit for handling memory access request is described. The circuit includes a receive memory device to temporarily store physical packets, including memory access requests from a bus. The physical packets include write requests. A posted write error queue is coupled to the receive memory device. The posted write error queue stores physical write requests for processing when a physical write request that was handled as a posted write request fails. A physical response queue also coupled to the memory device continues to accept non-posted write packets when the posted write error queue is full.